Answer: an OR gate

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Answer: 2^n - 1

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Answer: NOR or NAND gates

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Answer: Volatile

Explanation: Volatile Memory : A device which holds the data as long as it has power supply connected to it and cannot hold the memory when there is no power supply connected to it is called Volatile Memory. The best example for this can be Random Access Memory ( RAM ), which will hold memory only as long as it is connected to power source and everything in it will be cleared if it gets disconnected from power source. Volatile memory is also called as temporary memory as it will hold memory temporarily. Non Volatile Memory : A device which can hold data in it even if it is not connected to any power source is called Non Volatile Memory. The typical examples for Non Volatile Memory are your Hard drives and flash drives. Even if you turn off your PC the data in your hard drive or flash drive stays intact.

Answer: JK FF

Explanation: JK flipflop has three inputs and two outputs. Outputs are complementary to each other. when j = k = 0 and clk = 1; output of AND gates will be 0; when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output. when j =0 k =1 and clk = 1; output of AND gate connected to K will be Q and corresponding NOR gate output will be 0; which RESETs the flipflop. when j =1 k = 0 and clk = 1; output of AND gate connected to j will be Qbar and corresponding NOR gate output will be 0; which the SETs the flipflop. when j =1 k = 1 and clk = 1; Q output will toggle as long as CLK is high.Thus the output will be unstable creating a race-around problem with this basic JK circuit. This problem is avoided by ensuring that the clock input is at logic 1 only for a very short time, or to produce a more sophisticated JK flip-flop circuit called a Master slave flip-flop.

Answer: AND

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Answer: 3

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Answer: 3

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Answer: 2

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Answer: 1

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Answer: 1

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Answer: 4

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Answer: 4

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Answer: 4

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Answer: 4

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Answer: 5

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Answer: 5

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Answer: not sensitive to electrostatic discharge

Explanation: Characteristics of CMOS logic: Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays. Noise immunity approaches 50% or 45% of the full logic swing. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high. Voltage levels range from 0 to VDD where VDD is the supply voltage. A low level is anywhere between 0 and 1/3 VDD while a high level is between 2/3 VDD and VDD. Characteristics of TTL logic: Power dissipation is usually 10 mW per gate. Propagation delays are 10 nS when driving a 15 pF/400 ohm load. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1. CMOS compared to TTL: CMOS components are typically more expensive than TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design. Due to longer rise and fall times, the transmission of digital signals becomes simpler and less expensive with CMOS chips. CMOS components are more susceptible to damage from electrostatic discharge than TTL components.

Answer: 8

Explanation: 2^n states

Answer: 0011 0100 0111

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