RAM

AIM:Design and implement a RAM.

DESIGN Verilog Program- Random Acess Memory

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: RAM
// Project Name: Random Acess Memory
///////////////////////////////////////////////////////////////////////////
module ram(data,clk,reset,cs,we,addr,out);
input [3:0] data,addr;
input clk,reset,cs,we;
output reg [3:0] out;
reg [3:0] ram[0:15];
always @(*)
begin
if(cs)
if(we)
begin
ram[addr]=data;
out=4'bzzzz;
end
else
out=ram[addr];
else
out=4'bzzzz;
end
endmodule

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