Sequence Detector 0x01 Mealy implementation

AIM:Design and implement a Sequence Detector 0x01 Mealy implementation.

DESIGN VHDL PROGRAM

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: SequenceDetectorMealy
// Project Name: Sequence Detector 0x01 Mealy implementation
///////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------
entity EXP4a is
Port ( X : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : out STD_LOGIC);
end EXP4a;
----------------------------------------------------------
architecture Behavioral of EXP4a is
type state is (A, B, C, D, E);
signal CRNT,NXT: state;
begin
process(CLK,RST)
begin
if( RST = '1' ) then
CRNT <= A;
elsif (CLK'event and CLK= '1') then
CRNT<= NXT;
end if;
end process;

process (CLK,CRNT,X)
begin
case CRNT is
when A=>
if(X='0') then
Z<='0';
NXT<=B;
else
Z<='0';
NXT<=A;
end if;
when B=>
if(X='0') then
Z<='0';
NXT<=C;
else
Z<='0';
NXT<=E;
end if;
when C=>
if(X='0') then
Z<='0';
NXT<=D;
else
Z<='0';
NXT<=E;
end if;
when D=>
if(X='0') then
Z<='0';
NXT<=B;
else
Z<='1';
NXT<=C;
end if;
when E=>
if(X='0') then
Z<='0';
NXT<=D;
else
Z<='0';
NXT<=A;
end if;
end case;
end process;
end Behavioral;

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