8bit Up/Down Counter

AIM:Design and implement an 8bit Up/Down Counter with enable input and synchronous clear.

DESIGN

Verilog Program- Up Down Counter

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Up Down Counter
// Project Name: Up Down Counter
///////////////////////////////////////////////////////////////////////////
module UpDownCounter(clk,enable,reset,mode,count,tc);
input clk,enable,reset,mode;
output reg [7:0]count;
output reg tc;
always @(posedge clk)
begin
if(enable)
begin
if(reset)
begin
count=0;
tc=0;
end
else
begin
if(mode==0)
begin
count=count+1;
if(count==255)
tc=1;
else
tc=0;
end
else
begin
count=count-1;
<if(count==0)
tc=1;
else
tc=0;
end
end
end
end
endmodule

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