Verilog Program- Half Substractor

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Half Substractor
// Project Name: Half Substractor
///////////////////////////////////////////////////////////////////////////
module HalfSubstractor(a,b,difference,borrow);
input a,b;
output difference,borrow;
xor(difference,a,b);
assign borrow=(~a&b);
endmodule



Testbench Code- Half Substractor

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Half Substractor
// Project Name: Half Substractor
///////////////////////////////////////////////////////////////////////////
module TestModule;
// Inputs
reg a;
reg b;

// Outputs
wire difference;
wire borrow;

// Instantiate the Unit Under Test (UUT)
HalfSubstractor uut (
.a(a),
.b(b),
.difference(difference),
.borrow(borrow)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish
#100;

a = 1;
b = 0;

end
endmodule

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