Shift Register SIPO

DESIGN
Verilog Program- Shift Register SIPO

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: ShiftRegister_SIPO
// Project Name: Shift Register Serial Input Parallel Output
///////////////////////////////////////////////////////////////////////////
module ShiftRegister_SIPO(C, SI, PO);
input C,SI;
output [7:0] PO;
reg [7:0] tmp;

always @(posedge C)
begin
tmp = {tmp[6:0], SI};
end
assign PO = tmp;
endmodule


Shift Register PISO

DESIGN
Verilog Program- Shift Register PISO

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: ShiftRegister_PISO
// Project Name: Shift Register Parallel Input Serial Output
///////////////////////////////////////////////////////////////////////////
module Shiftregister_PISO(Clk, Parallel_In,load, Serial_Out);
input Clk,load;
input [3:0]Parallel_In;
output reg Serial_Out;
reg [3:0]tmp;
always @(posedge Clk)
begin
if(load)
tmp<=Parallel_In;
else
begin
Serial_Out<=tmp[3];
tmp<={tmp[2:0],1'b0};
end
end
endmodule


Shift Register PIPO

DESIGN
Verilog Program- Shift Register PIPO

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: ShiftRegister_PIPO
// Project Name: Shift Register Parallel Input Parallel Output
///////////////////////////////////////////////////////////////////////////
module ShiftRegister_PIPO(Clk,Pi,Po);
input Clk;
input [3:0]Pi;
output reg [3:0]Po;
always @(posedge Clk)
begin
Po = Pi;
end
endmodule

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