Sequence Detector Moore

AIM:Design a controller that detects the overlapping sequence “0X01” in a bit stream using moore machine.

DESIGN VHDL PROGRAM

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: SequenceDetectorMoore
// Project Name: Sequence Detector 0x01 Moore implementation
///////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MOORE4 is
Port ( X : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : out STD_LOGIC);
end MOORE4;

architecture Behavioral of MOORE4 is
type state is (A, B, C, D, E, F);
signal CRNT,NXT: state;
begin
process(CLK,RST)

begin
if( RST = '1' ) then
CRNT <= A;
elsif (CLK'event and CLK= '1') then
CRNT<= NXT;
end if;
end process;

process (CLK,CRNT,X)
begin
case CRNT is
when A=>
Z<='0';
if(X='0') then
NXT<=B;
else
NXT<=A;
end if;
when B=>
Z<='0';
if(X='0') then
NXT<=C;
else
NXT<=E;
end if;
when C=>
Z<='0';
if(X='0') then
NXT<=D;
else
NXT<=E;
end if;
when D=>
Z<='0';
if(X='0') then
NXT<=C;
else
NXT<=F;
end if;
when E=>
Z<='0';
if(X='0') then
NXT<=D;
else
NXT<=A;
end if;
when F=>
Z<='1';
if(X='0') then
NXT<=D;
else
NXT<=A;
end if;
end case;
end process;
end Behavioral;

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