Verilog Program- JK Flipflop

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: JKFlipflop
// Project Name: JK Flipflop
///////////////////////////////////////////////////////////////////////////
module JKFlipflop(J,K,clk,reset,q);
input J,K,clk,reset;
output q;
wire w;
assign w=(J&~q)|(~K&q);
D_Flipflop dff(w,clk,reset,q);
endmodule

module D_Flipflop(Din,clk,reset,q);
input Din,clk,reset;
output reg q;
always@(posedge clk)
begin
if(reset)
q=1'b0;
else
q=Din;
end
endmodule

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