Verilog Program for 1:8 Demultiplexer

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: 1:8 Demultiplexer
// Project Name: 1:8 Demultiplexer
///////////////////////////////////////////////////////////////////////////
module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule



Testbench Code for 1:8 Demultiplexer

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: 1:8 Demultiplexer
// Project Name: 1:8 Demultiplexer
///////////////////////////////////////////////////////////////////////////
module TestModule;
// Inputs
reg in;
reg s0;
reg s1;
reg s2;

// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

// Instantiate the Unit Under Test (UUT)
Demultiplexer uut (
.in(in),
.s0(s0),
.s1(s1),
.s2(s2),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;
// Wait 100 ns for global reset to finish
#100;
in = 1;
s0 = 0;
s1 = 1;
s2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule

.................................................................................................
Related Programs:
Verilog program for Basic Logic Gates
Verilog program for Half Adder
Verilog program for Full Adder
Verilog program for 4bit Adder
Verilog program for Half Substractor
Verilog program for Full Substractor
Verilog program for 4bit Substractor
Verilog program for Carry Look Ahead Adder
Verilog program for 3:8 Decoder
Verilog program for 8:3 Encoder
Verilog program for 1:8 Demultiplxer
Verilog program for 8:1 Multiplexer
Verilog program for 8bit D Flipflop
Verilog program for T Flipflop
Verilog program for JK Flipflop
Verilog program for Equality Comparator
Verilog program for 8bit Up down counter
Verilog program for 8bit Shift Register (SIPO,PISO,PIPO)
Verilog program for Random Access Memory(RAM)
Verilog program for Programmable clock Generator
Verilog program for Finite State Machine (mealy)
Verilog program for Finite State Machine (moore)