Random Acess Memory

AIM:Design and implement a RAM.

DESIGN

VHDL PROGRAM

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: RAM
// Project Name: Random Acess Memory
///////////////////////////////////////////////////////////////////////////
BLOCK 1: BUFFER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL
---------------------------------------------------------------------------
entity BFR is
Port ( IN0 : in STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
EN : in STD_LOGIC;
OP0 : out STD_LOGIC;
OP1 : out STD_LOGIC;
OP2 : out STD_LOGIC;
OP3 : out STD_LOGIC);
end BFR;
---------------------------------------------------------------------------
architecture Behavioral of BFR is
begin
process(EN, IN0,IN1,IN2,IN3)
begin
if (EN='0') then
OP0<='Z';
OP1<='Z';
OP2<='Z';
OP3<='Z';
else
OP0<=IN0;
OP1<=IN1;
OP2<=IN2;
OP3<=IN3;
end if;
end process;
end Behavioral;

BLOCK 2: DECODER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
----------------------------------------------------------------------------
entity DCDR is
Port ( A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
DLOC : out INTEGER);
end DCDR;
----------------------------------------------------------------------------
architecture Behavioral of DCDR is
signal adrs: STD_LOGIC_VECTOR (0 to 3);
begin
process(A0,A1,A2,A3,adrs)
begin
adrs<=A0 & A1 & A2 & A3;
DLOC<= CONV_INTEGER (adrs);
end process;
end Behavioral;

BLOCK 3: MEMORY
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------
entity MEMRY is
Port ( dloc : in integer;
din: in STD_LOGIC_VECTOR(0 to 3);
WE : in STD_LOGIC;
CS : in STD_LOGIC;
dout: out STD_LOGIC_VECTOR(0 to 3));
end MEMRY;
----------------------------------------------------------------------------
architecture Behavioral of MEMRY is
type address is array(0 to 15) of std_logic_vector(3 downto 0);
signal D: address ;
begin
process (WE,CS,din,D)
begin
if (CS='1') then
dout<="ZZZZ";
else
if (WE='0') then
D(dloc)<= din;
dout<="ZZZZ";
else
dout <=D(dloc);
end if;
end if;
end process;
end Behavioral;

BLOCK 4: INVERTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------------------------
entity INVT is
Port ( DAT : in STD_LOGIC_VECTOR (0 to 3);
I0 : out STD_LOGIC;
I1 : out STD_LOGIC;
I2 : out STD_LOGIC;
I3 : out STD_LOGIC);
end INVT;
------------------------------------------------------------------------
architecture Behavioral of INVT is
begin
process(DAT)
begin
if(DAT="ZZZZ") then
I0<=DAT(0);
I1<=DAT(1);
I2<=DAT(2);
I3<=DAT(3);
else
I0<=not DAT(0);
I1<=not DAT(1);
I2<=not DAT(2);
I3<=not DAT(3);
end if;
end process;
end Behavioral;

MAIN MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------
entity EXP7 is
Port ( WE : in STD_LOGIC;
CS : in STD_LOGIC;
A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
D0 : in STD_LOGIC;
D1 : in STD_LOGIC;
D2 : in STD_LOGIC;
D3 : in STD_LOGIC;
O0 : out STD_LOGIC;
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC);
end EXP7;
---------------------------------------------------------------------------
architecture Behavioral of EXP7 is
signal tin,tout,tmp: std_logic_vector(0 to 3);
signal dloc:integer;
signal EN1,EN2: std_logic;
component BFR is
Port ( IN0 : in STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
EN : in STD_LOGIC;
OP0 : out STD_LOGIC;
OP1 : out STD_LOGIC;
OP2 : out STD_LOGIC;
OP3 : out STD_LOGIC);
end component;
component DCDR is
Port ( A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
DLOC : out INTEGER);
end component;
component MEMRY is
Port ( dloc : in integer;
din: in STD_LOGIC_VECTOR(0 to 3);

WE : in STD_LOGIC;
CS : in STD_LOGIC;
dout: out STD_LOGIC_VECTOR(0 to 3));
end component;
component INVT is
Port ( DAT : in STD_LOGIC_VECTOR (0 to 3);
I0 : out STD_LOGIC;
I1 : out STD_LOGIC;
I2 : out STD_LOGIC;
I3 : out STD_LOGIC);
end component;
begin
EN1<=(not CS) and (not WE);
EN2<=(not CS) and WE;
B1: BFR port map (D0,D1,D2,D3,EN1,tin(0),tin(1),tin(2),tin(3));
DC1: DCDR port map (A0,A1,A2,A3,dloc);
M1: MEMRY port map(dloc,tin,WE,CS,tout);
B2: BFR port map (tout(0),tout(1),tout(2),tout(3),EN2,tmp(
0),tmp(1),tmp(2),tmp(3));
I1: INVT port map (tmp,O0,O1,O2,O3);
end Behavioral;

.................................................................................................
Related Programs:
Random Access Memory
Sequence Detector(Moore)
Sequence Detector(Mealy)
Programmable Clock Generator