Verilog Program- Logic Gates
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Logic Gates
// Project Name: Logic Gates
///////////////////////////////////////////////////////////////////////////
module LogicGates(a,b,y1,y2,y3,y4,y5,y6,y7);
input a,b;
output y1,y2,y3,y4,y5,y6,y7;
and(y1,a,b);
or(y2,a,b);
not(y3,a);
nand(y4,a,b);
nor(y5,a,b);
xor(y6,a,b);
xnor(y7,a,b);
endmodule
Testbench Code- Logic Gates
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Logic Gates
// Project Name: Logic Gates
///////////////////////////////////////////////////////////////////////////
module TestModule;
// Inputs
reg a;
reg b;
// Outputs
wire y1;
wire y2;
wire y3;
wire y4;
wire y5;
wire y6;
wire y7;
// Instantiate the Unit Under Test (UUT)
LogicGates uut (
.a(a),
.b(b),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4),
.y5(y5),
.y6(y6),
.y7(y7)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100
a = 1;
b = 0;
end
endmodule
.................................................................................................
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