8BIT D FLIPFLOP

AIM:Design and implement an 8bit d-flipflop with enable input and synchronous clear.

DESIGN

Verilog Program- 8bit DFlipflop

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: 8bit DFlipflop
// Project Name: 8bit DFlipflop
///////////////////////////////////////////////////////////////////////////
module DFlipflop(Din,clk,clear,enable,Q);
input [7:0]Din;
input clk,clear,enable;
output reg [7:0] Q;
always@(posedge clk)
if(enable)
begin
if(clear)
Q<=0;
else
Q<=Din;
end
endmodule

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