Verilog Program- 4bit Adder

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: 4bit Adder
// Project Name: 4bit Adder
///////////////////////////////////////////////////////////////////////////
module MultibitAdder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0]sum;
output cout;
assign {cout,sum}=a+b+cin;
endmodule



Testbench Code- 4bit Adder

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: 4bit Adder
// Project Name: 4bit Adder
///////////////////////////////////////////////////////////////////////////
module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;


// Instantiate the Unit Under Test (UUT)
MultibitAdder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;

a = 2;
b = 3;
cin = 1;

// Wait 100 ns for global reset to finish
#100

end
endmodule

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