By configuring the DAC (digital to analog converter) , we can generate sine wave of required frequency.
The DAC used in LPC 1769 has the following features.
1. 10-bit digital to analog converter
2. Resistor string architecture
3. Buffered output
4. Selectable speed vs. power
5. Maximum update rate of 1 MHz.
Analog Output(AOUT)- After the selected settling time after the DACR is written with a new value, the voltage on this pin (with respect to VSSA) is VALUE ((VREFP - VREFN)/1024) + VREFN. The DAC output is disabled when the device is in deep-sleep, power-down, or deep power-down mode.
Voltage References (VREFP, VREFN)- These pins provide a voltage reference level for the ADC and DAC. VREFP should be tied to VDD (3V3) and VREFN should be tied to VSS if the ADC and DAC are not used.
Analog Power and Ground (VDDA, VSSA)- These should typically be the same voltages as VDD and VSS, but should be isolated to minimize noise and error. Note: VDDA should be tied to VDD(3V3) and VSSA should be tied to VSS if the ADC and DAC are not used.
This read/write register includes the digital value to be converted to analog, and a bit that trades off performance vs. power. Bits 5:0 are reserved for future, higher-resolution D/A converters.
Bit[5:0] - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
BIT[15:6] (value)- After the selected settling time after this field is written with a new VALUE, the voltage on the AOUT pin (with respect to VSSA) is VALUE ((VREFP - VREFN)/1024) + VREFN.
BIT[16] (bias)- When bit 16 is 0, the settling time of the DAC is 1 microsecond max, and the maximum current is 700 microampere. This allows a maximum update rate of 1 MHz. Bit 16 as 1 The settling time of the DAC is 2.5 microsecond and the maximum current is 350 microampere . This allows a maximum update rate of 400 kHz.
BIT[31:17] – Reserved
This register contains the reload value for the DAC DMA/Interrupt timer.